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preliminary W45B010 1m 1 serial flash memory publication release date: february 2 2 , 2002 - 1 - revision a1 general description the W45B010 is manufactured with winbond?s high performance cmos winflash technology. the serial flash is organized as 32 sectors of 4096 bytes for the W45B010. the memory is accessed for read or erase/program by the spi bus compatible serial protocol. the bus signals are: serial data input (si), serial data output (so), serial clock (sck), write protect (#wp), chip enable (#ce), and hardware reset (#reset). this device is offered in 8l son and 32l plcc package. features single 2.7 - 3.6v read and write operations serial interface architecture - spi compatible: mode 0 and mode 3 byte serial read with single command superior reliability - endurance: 10,000 cycles (typ.) - 20 years data retention low power consumption - active current: 30 ma (max) - standby current: 15 m a (max) sector or chip - era se capability - uniform 4 kbyte sectors fast erase and byte - program - chip - erase time: 100 ms (max.) - sector - erase time: 25 ms (max.) - byte - program time: 50 m s (max.) automatic write timing - inte rnal v pp generation end - of - write detection - software status 2 0 mhz max clock frequency hardware reset pin (#reset) - resets the device to standby mode ttl compatibility hardware data protection - protects/unprotects the device from write operation packages available 8l son (5 x 6 mm) , 32l plcc
preliminary W45B010 - 2 - pin configurations 1 2 3 4 8 7 6 5 8l son top view #reset vss so si #wp vdd #ce sck s c k 5 6 7 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 n c v d d 32l plcc n c n c nc nc #reset # c e n c nc nc nc nc nc nc nc si s 0 v s s n c n c n c n c nc nc nc nc nc nc nc # w p block diagram superflash cell array x-decoder address buffers and latches y-decoder control logic i/o buffers and data latches serial interface #ce sck si so #wp #reset pin description symbol pin name #ce chip enable si serial data input so serial data output sck serial clock #wp write protect #reset reset v dd power supply v ss ground product identificati on byte data manufacturer?s id 0000 h da h device id: w4 5b010 0001 h 91 h
preliminary W45B010 publication release date: february 2 2 , 2002 - 3 - revision a1 functional descripti on device operation the W45B010 uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. the operation instructions are listed i n the table below. all instructions are synchronized off a high to low transition of #ce. the first low to high transition on sck will initiate the instruction sequence. inputs will be accepted on the rising edge of sck starting with the most significant b it. any low to high transition on #ce before the input instruction completes will terminate any instruction in progress and return the device to the standby mode. read the read operation outputs the data in order from the initial accessed address. while sc k is input, the address will be incremented automatically until end (top) of the address space, then the internal address pointer automatically increments to beginning (bottom) of the address space (00000h), and data out stream will continue. the read data stream is continuous through all addresses until terminated by a low to high transition on #ce. sector/chip - erase operation the sector - erase operation clears all bits in the selected sector to ?ff?. the chip - erase instruction clears all bits in the device to ?ff?. byte - program operation the byte - program operation programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (?ff?) when initiating a program operation. the data is input from bit 7 to bit 0 in order . software status operation the status operation determines if an erase or program operation is in progress. if bit 0 is at a ?0? an erase or program operation is in progress, the device is busy. if bit 0 is at a ?1? the device is ready for any valid opera tion. the status read is continuous with ongoing clock cycles until terminated by a low to high transition on #ce. reset reset will terminate any operation, e.g., read, erase and program, in progress. it is activated by a high to low transition on the #res et pin. the device will remain in reset condition as long as #reset is low. minimum reset time is 10 m s. see figure 14 for reset timing diagram. #reset is internally pulled - up and could remain unconnected during normal operation. after reset, the device is in standby mode, a high to low transition on #ce is required to start the next operation. an internal power - on reset circuit protects against accidental data writes. applying a logic level low to #reset during the power - on process then changing to a logic level high when v dd has reached the correct voltage level will provide additional protection against accidental writes during power on. read winbond id/read device id the read manufacturer id and read device id operations read the jedec assigned manufactu rer identification and the manufacturer assigned device identification codes. these codes may be used to determine the actual device resident in the system.
preliminary W45B010 - 4 - write protect the #wp pin provides inadvertent write protection. the #wp pin must be held high for any erase or program operation. the #wp pin is ?don?t care? for all other operations. in typical use, the #wp pin is connected to v ss with a standard pull - down resistor. #wp is then driven high whenever an erase or program operation is required. if the #wp pin is tied to v dd with a pull - up resistor, then all operations may occur and the write protection feature is disabled. the #wp pin has an internal pull - up and could remain unconnected when not used. device operation ins truction bus cycle 1 2 3 4 5 6 7 o peration/type command address 1 address address data dummy data read ffh a 2 3 - a 16 a 15 - a 8 a 7 - a 0 x x dout sector - erase 2 20h a 2 3 - a 16 a 15 - a 8 x dout x chip - erase 60h x x x dout x byte - program 10h a 2 3 - a 16 a 15 - a 8 a 7 - a 0 din x software - statu s 9fh dout read manufacture id 90h x x a 0 = 0 dah read device id 3 90h x x a 0 = 1 91h notes: 1. a2 3 - a17 are ?don't care? for device. 2. a1 6 - a12 are used to determine sector address, a1 1 - a8 are don't care. 3. with a1 6 - a1 = 0, W45B010 dev ice id = 91h, is read with a0 = 1. device operation tab le operation si so #ce 1 #wp #reset read x dout low x high sector - erase x x low high high chip - erase x x low high high byte - program din x low high high software - status x dout low x high reset 2 x x x x low read manufacture id x dout low x high read device id x dout low x high notes: 1. a high to low transition on #ce will be required to start any device operation except for reset. 2. the #reset low will return the device to standby and terminate any erase or program operation in progress.
preliminary W45B010 publication release date: february 2 2 , 2002 - 5 - revision a1 dc characteristics absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only an d functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) parameter rating unit temperature under bias - 55 to +125 c storage temperature - 65 to +150 c d. c. voltage on any pin to ground potential - 0.5 to v dd +0.5 v transient voltage (<20 ns) on any pin to ground potential - 1.0 to v dd +1.0 v package power dis sipation capability (t a = 25 c) 1.0 w surface mount lead soldering temperature (3 seconds) 240 c output short circuit current 1 50 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc operating characteristics (v dd =2.7v - 3.6v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test condition min. max. units program/erase - 30 ma power supply current i dd f = 20 mhz, #ce = v i l, v dd = v dd max. read - 20 ma standby current i sb #ce = v ihc , v dd = v dd max. - 15 m a input leakage output leakage i li i lo v in = gnd to v dd , v dd = v dd max. v out = gnd to v dd , v dd =v dd max. - 2 2 m a m a input low voltage v il - 0.2 0.6 v input high voltage v ih 2.0 v dd +0.3 v output low voltage v ol i ol = 1.6 ma - 0.4 v output high volt age v oh i oh = - 0.4 ma 2.4 - v note: outputs shorted for no more than one second. no more than one output shorted at a time.
preliminary W45B010 - 6 - capacitance (v dd = 2.7v - 3.6v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit output pin capacitance c out 1 v dq = 0v 12 pf input pin capacitance c in 1 v in = 0v 6 pf ac characteristics ac test conditions (v dd = 2.7v - 3.6v) parameter conditions input rise/fall time <5 ns input/output timing level 0.5 v dd / 0.5 v dd output load c l = 30 pf ac test load and waveform c l =30pf input reference points output v iht v ilt v it v ot ac test inputs are driven at v iht (0.9 v d d ) for a logic ?1? and v ilt (0.1 v d d ) for a logic ?0?.measurement reference points for inputs and outputs are at v it (0.5 v d d ) and v ot (0.5 v d d ) input rise and fall times (10% ? 90%) are <5 ns . note: v i t : vinput test; v o t : voutput test; v ih t : vinput high test; v il t ; vinput low test
preliminary W45B010 publication release date: february 2 2 , 2002 - 7 - revision a1 ac operating characteristics (v dd = 2.7v - 3.6v) limits parameter symbol min. max. units serial clock frequency f clk 20 mhz serial clock high time t sckh 22 - ns serial clock low time t sckl 22 - ns #ce setup time t ces 10 - ns #ce hold time t ceh 10 - ns #ce high time t cph 50 - ns #ce high to high - z output t chz - 20 ns #ce low to low - z output t clz 0 - ns #reset low to high - z output t rlz - 20 ns data in setup time t ds 5 - ns data in hold time t dh 5 - ns output hold from sck change t oh 0 - ns output valid from sck t v - 25 ns write protect setup time t wps 10 - ns write protect hold time t wph 10 - ns sector - erase t se - 25 ns chip - erase t sce - 100 ms byte - program t bp - 50 m s reset pulse width t rst 10 - m s reset recovery time t rec - 1 m s reset time after power - up t purst 10 - m s
preliminary W45B010 - 8 - timing waveforms serial input timing diagram (inactive serial clock low - mode 0) data valid high-z high-z t ceh t cph t ces t t ds dh #wp #ce sck si so t t sckh sckl serial output tim ing diagram (inactive serial clock low - mode 0) data valid sckh t sckl t t oh t clz t t ceh chz #wp #ce sck so si t v serial input timing diagram (inactive serial clock high - mode 3) ces t sckh sckl t t ds dh t t high-z high-z data valid ceh t cph t #ce sck si so #wp
preliminary W45B010 publication release date: february 2 2 , 2002 - 9 - revision a1 timing waveforms, continued serial output timing diagram (inactive serial clock high - mode 3) sckh t sckl t clz t data valid t v t oh t t ceh chz #wp #ce sck so si sector - erase timing diagram high impedance add . add . x x d0h 0 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 t wph t wps self-timed sector- erase cycle #wp #ce sck si so
preliminary W45B010 - 10 - timing waveforms, continued chip - erase timing diagram #wp #ce sck si so high impedance x x d0h 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 t wph t wps self-timed sector- erase cycle t sce 1 x x byte - program timing diagram high impedance 15 0 1 2 3 4 5 6 7 8 16 23 24 31 32 39 40 47 t wph t wps self-timed sector- erase cycle t bp #wp #ce sck si so x din 0 0 0 0 0 1 0 0 add. add. add. msb lsb
preliminary W45B010 publication release date: february 2 2 , 2002 - 11 - revision a1 timing waveforms, continued read timing diagram 0 1 2 3 4 5 6 7 8 16 23 24 31 32 39 40 15 47 55 48 56 63 64 71 x 0 0 0 0 0 1 0 0 add. add. add. x high impedance #wp #ce sck si so dout dout dout msb msb msb n n+1 n+2 read - id timing diagram 0 1 2 3 4 5 6 7 8 16 23 24 31 32 39 40 15 47 55 48 56 63 64 71 x 0 0 0 0 1 0 0 add high impedance #wp #ce sck si so dout msb lsb 1 x 1 note: 1. manufacturer's id = dah is read with a 0 = 0 device id = 91h is read with a 0 = 1
preliminary W45B010 - 12 - timing waveforms, continued software - status timing diagram 0 1 2 3 4 5 6 7 8 11 13 14 24 10 1 0 0 high impedance #wp #ce sck si so msb 1 9 12 15 16 23 31 1 1 1 1 data data data msb msb reset timing diagram (in active clock polarity low shown) high impedance t rlz t t t rec rst ces high impedance #ce sck si so #reset
preliminary W45B010 publication release date: february 2 2 , 2002 - 13 - revision a1 timing waveforms, continued power - on reset timing diagram t purst t rec v dd #reset #ce write protect timing diagram t t t t t wps ces wph cph ceh #wp #ce sck
preliminary W45B010 - 14 - ordering information part no. operating voltage (v) power supply current max. ( m a) standby v dd current max. ( m a) package cycling operating temp. ( c) w4 5b010z 2.7v - 3.6v 30 15 8l son (5 x 6 mm) 10k 0 c - 70 c w4 5b010p 2.7v - 3.6v 30 15 32l plcc 10k 0 c - 70 c notes: 1. winbond reserves the right to make changes to i ts products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. how to read the top m arking example: the top marking of 32l - plcc W45B010z 1 st line: winbond logo 2 nd line: the part number: W45B010z 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: p ackages made in ?01, week 49 o: assembly house id: a means ase, o means ose, ... etc. b: ic revision; a means version a, h means version h, ... etc. sa: process code W45B010z 2138977a - a12 149obsa
preliminary W45B010 publication release date: february 2 2 , 2002 - 15 - revision a1 package dimensions 8l son (5 x 6 mm) 32l plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
preliminary W45B010 - 16 - version history version date page description a1 feb. 2 2 , 2002 - initial issue headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 min-sheng east. rd.,

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